FPGA and VHDL Consulting
Sami Muurinaho is a consultant engaged in demanding electronics industry projects involving FPGA circuits. His specialist expertise focuses on planning, auditing and problem-resolving tasks related to the use of FPGA circuits.
The accumulated experience covers comprehensively data transfer, encryption and signal processing IP blocks.
The main benefit to be gained from using a consultant in problem resolving situations is where the customer perceives a system malfunction, but is not able to resolve it using in-house resources. An experienced consultant provides a review of the system being developed and this works as a means of finding explanations for malfunctions already detected and it constitutes an important aspect of quality assurance before the finished product is put into practical use. Often such a review also reveals risks that shall be avoided, but which cannot be revealed with the testing methods applied so far.
The way in which VHDL is used by the planning team has to be consistent and compliant with updated and approved style guidelines. Adhering to a common set of style guidelines enhances the reviewing of on-going planning tasks and reduces the risk of errors getting past testing phases into field application, in which case remedial costs would be significant.
In addition to project-specific tasks, we organize training on the best uses of VHDL. These training sessions are tailored to meet each customer's needs. The primary training objectives are as follows: to enhance reusability, to take clocking solutions into account in the proper way and to minimize the time required for testing manufactured physical devices. When these objectives are achieved, the quality of the system implementation improves, the scope of the testing improves and the risk of subsequent extra costs is reduced.
We deliver our services either at the customer’s premises or at Midir Oy’s premises. Our pricing is time-based.
VHDL Example Design
The released example design illustrates VHDL coding style and it can be used as the basis when updating in-house VHDL style guidelines. The example design is open source code and it is published under the [GNU LGPL] license. The example design consists of two parts:
- VHDL IP Block
Midir_ALED is a VHDL IP block, which measures the signal’s activity and shows the results using LEDs. The application of the IP block can be just a LED blinker or even a speed indicator with 7-segment displays.
- Device Specific Configuration
The following three optional configurations show a Midir_ALED IP block being used for measuring Ethernet bandwidth reservation. The results are shown using a PCB’s LED components or 7-segment displays.
Midir_BeMicro_SDK is the device specific example design for Altera Cyclone IV FPGA device on BeMicro SDK development card. Altera Quartus II software is used in compiling the source code.
Midir_LX9_MicroBoard is the device specific example design for Xilinx Spartan-6 FPGA device on Avnet Spartan-6 LX9 MicroBoard development card. Xilinx ISE software is used in compiling the source code.
Midir_LatticeMico32 is the device specific example design for Lattice ECP2 FPGA device on LatticeMico32 development card. Lattice Diamond software is used in compiling the source code.
The example design and more information about development cards can be downloaded from the following links: